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This chapter introduces the register transfer methodology, which describes system operation by a sequence of data transfers and manipulations among registers, and demonstrates the construction of the data path (a regular sequential circuit) and the control path (an FSM) used in this methodology. | Register Transfer Methodology I RTL Hardware Design by P. Chu Chapter 11 1 Outline 1. Introduction 2. Overview of FSMD 3. FSMD design of a repetitive-addition multiplier 4. Alternative design of a repetitiveaddition multiplier 5. Timing and performance analysis of FSMD 6. Sequential add-and-shift multiplier RTL Hardware Design by P. Chu Chapter 11 2 1. Introduction • How to realize an algorithm in hardware? • Two characteristics of an algorithm: – Use of variables (symbolic memory location) e.g., n = n + 1 in C – Sequential execution (execution order is important) RTL Hardware Design by P. Chu Chapter 11 3 • E.g., an algorithm: – Summate 4 number – Divide the result by 8 – Round the result • Pseudocode RTL Hardware Design by P. Chu Chapter 11 4 • “Dataflow” implementation in VHDL – Convert the algorithm in to combinational circuit – No memory elements – The sequence is embedded into the “flow of data” RTL Hardware Design by P. Chu Chapter .
