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IA32 Paging Scheme products about Several ‘paging’ schemes, Control Register CR3, Two-Level Translation Scheme, Format of a Page-Table entry, The Error-Code format, Control Register CR2, Multiple Logical Processors. | IA32 Paging Scheme Introduction to the Intel x86’s support for “virtual” memory What is ‘paging’? • It’s a scheme for dynamically remapping addresses for fixed-size memory-blocks Physical address-space Virtual address-space What’s ‘paging’ good for? • For efficient ‘time-sharing’ among multiple tasks, an operating system needs to have several programs residing in main memory at the same time • To accomplish this using actual physical memory-addressing would require doing address-relocation calculations each time a program was loaded (to avoid conflicting with any addresses already being used) Why use ‘paging’? • Use of ‘paging’ allows ‘relocations’ to be done just once (by the linker), and every program can ‘reuse’ the same addresses Task #3 Task #1 physical memory Task #2 Several ‘paging’ schemes • Intel’s design for ‘paging’ has continued to evolve since its introduction in 80386 CPU • New processors support the initial design, as well as several optional extensions • We shall describe the initial design which is simplest and remains as the ‘default’ • It is based on subdividing the entire 4GB virtual address-space into 4KB .
