TAILIEUCHUNG - Development of a many core architecture for automotive embedded systems
The many-core evaluation platform is implemented on FPGA utilizing multiple massproduced evaluation boards, which can result to several advantages such as low cost of development, flexibility and easy implementation as compared to that of manufacturing in a real LSI chip. | Journal of Automation and Control Engineering Vol. 4, No. 2, April 2016 Development of a Many-core Architecture for Automotive Embedded Systems Trung-Dung Pham, Van-Tien Nguyen, and Truong-Son Nguyen Department of Control Engineering, Le Quy Don Technical University, Hanoi, Vietnam Email: thchdung@, {tiendiep73, sonhuongjp}@ for the system-on-a-chip designs. A multi-core processor named OSCAR and its automatic parallelization compiler is introduced in [1] and [2]. Besides, an actual multi-core chip with the ability of reducing power consumption by an automatic parallelizing compiler is also developed [3]. A coherence control mechanism by compiler for manycore processors is proposed in [4]. However, these architectures do not adopt a NoC-based structure which is a very significant aspect of many-core processors. In practice, it is hard to extend to hundreds of cores in such a bus-based architecture. Thanks to the advance of technology, nowadays, many experimental products as well as commercial products of the NoC-based many-core processor with several tens to hundreds of cores are becoming practical. In 2008, Intel Inc. has introduced a processor with 80 cores for experiment, which one tera FLOPS or more can be achieved [5]. The floating point cores in this processor are built in the 8x10 two-dimensional mesh network. In 2010, a many-core processor called ATAC [6] built from 1024 cores that can provide a high-speed global broadcasting network using an on-chip optical network is proposed. A scalable directory-based cache coherence protocol called ACKwise using the optical network is developed for improving ATAC processor performance. At the same time, the TILE64 of Tilera Inc. [7] has been provided as a commercial many-core processor. In TILE64, 8x8 homogeneous cores are organized in a mesh on-chip network called iMesh. Since these processors are implemented in the real LSI chips, they require very high cost of development and implementation. .
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