TAILIEUCHUNG - Digital Media Processors

As a result of this increased activity delivering tangible results, we increased our shipment and megawatt fi gures for the full year of 2011, and have adopted a more optimistic forecast for 2012. There have been many announcements in the fi rst half of 2012, including a number of fuel cell companies increasing their production capacity. We see this move as a very positive sign that the commercial sales volumes announced in a number of sectors will indeed be delivered according to planned timescales. One particularly positive example is the continued evolution of the deal between FuelCell Energy and POSCO. | Texas Instruments DM3730 DM3725 --------------------- DM3730 DM3725 Digital Media Processors Check for Samples DM3730 DM3725 1 DM3730 DM3725 Digital Media Processors Features DM3730 25 Digital Media Processors - Compatible with OMAP 3 Architecture - ARM Microprocessor MPU Subsystem Up to 1-Ghz arm CorteX -A8 Core Also supports 300 600 and 800-MHz operation NEON SIMD Coprocessor - High Performance Image Video Audio Accelerator Subsystem Up to 800-MHz TMS320c64x tm DSP Core Also supports 260 520 and 660-MHz operation Enhanced Direct Memory Access EDMA Controller 128 Independent Channels Video Hardware Accelerators - POWERVR SGX Graphics Accelerator DM3730 only Tile Based Architecture Delivering up to 20 MPoly sec Universal Scalable Shader Engine Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality Industry Standard API Support OpenGLES and Fine Grained Task Switching Load Balancing and Power Management Programmable High Quality Image Anti-Aliasing - Advanced Very-Long-Instruction-Word VLIW TMS320C64x TM DSP Core Eight Highly Independent Functional Units Six ALUs 32- 40-Bit Each Supports Single 32- bit Dual 16-bit or Quad 8-bit Arithmetic per Clock Cycle Two Multipliers Support Four 16 x 16-Bit Multiplies 32-Bit Results per Clock Cycle or Eight 8 x 8-Bit Multiplies 16-Bit Results per Clock Cycle Load-Store Architecture With Non-Aligned Support 64 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional Additional C64x TM Enhancements - Protected Mode Operation - Expectations Support for Error Detection and Program Redirection - Hardware Support for Modulo Loop Operation - C64x TM L1 L2 Memory Architecture 32K-Byte L1P Program RAM Cache Direct Mapped 80K-Byte Lid Data RAM Cache 2-Way Set- Associative 64K-Byte L2 Unified Mapped RAM Cache 4- Way Set-Associative 32K-Byte L2 Shared SrAm and 16K-Byte L2 ROM - C64x TM Instruction Set Features Byte-Addressable 8- 16- 32- 64-Bit Data

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