TAILIEUCHUNG - XTR Implementation on Reconfigurable Hardware

In this paper, we propose an efficient hardware implementation of this primitive that can be used for asymmetric digital signature, key exchange and asymmetric encryption. To our knowledge this is the first hardware implementation of XTR. | XTR Implementation on Reconfigurable Hardware Eric Peeters1 Michael Neve1 and Mathieu Ciet2 1 UCL Crypto Group Place du Levant 3 1348 Louvain-La-Neuve Belgium. peeters mneve @ http crypto 2 Innova Card Avenue Coriandre 13 600 La Ciotat France. Abstract. Recently Lenstra and Verheul proposed an efficient cryptosystem called XTR. This system represents elements of Fp6 with order dividing p2 p 1 by their trace over Fp2. Compared with the usual representation this one achieves a ratio of three between security size and manipulated data. Consequently very promising performance compared with RSA and ECC are expected. In this paper we are dealing with hardware implementation of XTR and more precisely with Field Programmable Gate Array FPGA . The intrinsic parallelism of such a device is combined with efficient modular multiplication algorithms to obtain effective implementation s of XTR with respect to time and area. We also compare our implementations with hardware implementations of RSA and ECC. This shows that XTR achieves a very high level of speed with small area requirements an XTR exponentiation is carried out in less than ms at a frequency beyond 150 MHz. Keywords Public key cryptosystem XTR reconfigurable hardware efficient implementation. 1 Introduction and Basics Nowadays more and more applications need security components. However these requirements should not interfere with the performance otherwise security would be disregarded. Ideally the best solution is when security does not penalize the application. However two ways are possible to achieve this characteristic design efficient primitive algorithms and or try to find fast and optimized implementations of existing algorithms. Supported by the FRIA Belgium fund. To appear in Cryptographic Hardware and Embedded Systems 2004 CHES04 proceedings IACR URL http comp lncs XTR first presented in 12 has been designed as a

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