TAILIEUCHUNG - Handbook of algorithms for physical design automation part 93

Handbook of Algorithms for Physical Design Automation part 93 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 902 Handbook of Algorithms for Physical Design Automation Conditioned local clocks FIGURE Alpha 21264 clock hierarchy. From Bailey . and Behschneider . IEEE J. Solid-State Circuits 33 1627 1998. With permission. FIGURE Global clock distribution network of Alpha 21264. From Bailey . and Behschneider . IEEE J. Solid-State Circuits 33 1627 1998. With permission. also helps power-supply and heat-dissipation problems. The GCLK grid is shown in Figure . It traverses the entire die and uses 3 percent of M3 and M4. All clock interconnect is laterally shielded with either VDD or 7SS. All clock wires and all lateral shields are manually placed. The measured GCLK skew is 65 ps running at 0 C ambient and V. The six major clocks are two gain stages past GCLK with grids juxtaposed with GCLK but shielded from it. The major clock grids are shown in Figure . Because of the wide variation of clock loads the grid density varies widely between major clocks and sometimes even for a single major clock. The densest areas use up to 6 percent of M3 and M4. Major clocks driven by a gridded global clock substantially reduce power because major clock drivers are localized to the clock loads and major clock grids are locally sized to meet the skew targets. A gridded global clock without major Practical Issues in Clock Network Design 903 FIGURE GCLK of Alpha 21264. From Bailey . and Behschneider . IEEE J. Solid-State Circuits 33 1627 1998. With permission. clocks would require larger drivers and a denser grid to deliver the same clock skew and edges. Major clocks are designed so that delay from GCLK is centered at 300 ps. The target specifications for skew are 50 ps. The target specifications for 10-90 percent rise and fall times are less than 320 ps. All major clocks easily meet both sets of objectives. FIGURE Six major clock grids of Alpha 21264. From Bailey . and Behschneider . IEEE J. Solid-State Circuits 33 1627 1998. With permission.

TỪ KHÓA LIÊN QUAN
TAILIEUCHUNG - Chia sẻ tài liệu không giới hạn
Địa chỉ : 444 Hoang Hoa Tham, Hanoi, Viet Nam
Website : tailieuchung.com
Email : tailieuchung20@gmail.com
Tailieuchung.com là thư viện tài liệu trực tuyến, nơi chia sẽ trao đổi hàng triệu tài liệu như luận văn đồ án, sách, giáo trình, đề thi.
Chúng tôi không chịu trách nhiệm liên quan đến các vấn đề bản quyền nội dung tài liệu được thành viên tự nguyện đăng tải lên, nếu phát hiện thấy tài liệu xấu hoặc tài liệu có bản quyền xin hãy email cho chúng tôi.
Đã phát hiện trình chặn quảng cáo AdBlock
Trang web này phụ thuộc vào doanh thu từ số lần hiển thị quảng cáo để tồn tại. Vui lòng tắt trình chặn quảng cáo của bạn hoặc tạm dừng tính năng chặn quảng cáo cho trang web này.