TAILIEUCHUNG - Fault Tolerant Computer Architecture-P13

Fault Tolerant Computer Architecture-P13: For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore’s law into remarkable increases in performance. Recently, however, the bounty provided by Moore’s law has been accompanied by several challenges that have arisen as devices have become smaller, including a decrease in dependability due to physical faults | 99 CHAPTER 6 The Future This book represents a snapshot of the field as of January 2009. Fault-tolerant computer architecture is a vibrant field that has been reinvigorated in the past 10 years or so by forecasts of increasing fault rates and we expect this field to evolve quite a bit in the upcoming years as the current reliability challenges become more acute and new challenges arise. The general concepts described in this book will not become obsolete but we expect and hope that many new ideas and implementations will be developed to address current and emerging challenges. In the four main chapters of this book we have identified some of the open problems to be solved and we anticipate that those problems as well as problems that have not even arisen yet will be tackled. ADOPTION BY INDUSTRY Despite the recent excitement about research in fault-tolerant computer architecture few of the products of this renaissance of research have thus far found their way into commodity processors. Industry is understandably reluctant to add anything seemingly complicated or costly until absolutely required and current fault rates have not yet led to enough user-visible hardware failures to persuade much of the industry that sophisticated fault tolerance is necessary. Industry has been willing to adopt fault tolerance mechanisms that provide a large bang for the buck such as adding low-cost parity to detect all single-bit errors in a cache but more sophisticated and costly fault tolerance mechanisms have been confined to mainframes supercomputers and mission-critical embedded processors. Nevertheless despite industry s current reluctance to adopt fault tolerance techniques industry is unlikely to be able to maintain that attitude. Fault rates are expected to increase dramatically in future generations of CMOS and future nanotechnologies that may replace CMOS are expected to be even less reliable. Processors implemented in such technologies are unlikely to be dependable .

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