TAILIEUCHUNG - Verilog interview questions with answers

CMOS interview questions. 1/ What is latch up? Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high amount of current to continuously flow through it once it is accidentally triggered or turned on. Depending on the circuits involved, the amount of current flow produced by this mechanism can be large enough to result in permanent destruction of the device due to electrical overstress (EOS). | VERILOG INTERVIEW QUESTIONS WITH ANSWERS . Write a Verilog code to swap contents of two registers with and without a temporary register With temp reg always @ posedge clock begin temp b b a a temp end Without temp reg always @ posedge clock begin a b b a end Difference between blocking and non-blocking Verilog interview questions that is most commonly asked The Verilog language has two forms of the procedural assignment statement blocking and non-blocking. The two are distinguished by the and assignment operators. The blocking assignment statement operator acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement. The non-blocking operator evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit. For example the following Verilog program testing blocking and non-blocking assignment module blocking reg 0 7 A B initial begin initl A 3 1A A 1 blocking procedural assignment B A 1 display Blocking A b B b . A B A 3 1A A 1 non-blocking procedural assignment B A 1 1 display Non-blocking A b B b . A B end VERILOG INTERVIEW QUESTIONS Lumos Page 1 VERILOG INTERVIEW QUESTIONS WITH ANSWERS . endmodule produces the following output Blocking A 00000100 B 00000101 Non-blocking A 00000100 B 00000100 The effect is for all the non-blocking assignments to use the old values of the variables at the beginning of the current time unit and to assign the registers new values at the end of the current time unit. This reflects how register transfers occur in some hardware systems. blocking procedural assignment is used for combinational logic and non-blocking procedural assignment for sequential Tell me about Verilog file I O OPEN A FILE integer file file fopenr filename file fopenw filename file fopena filename The function fopenr opens an existing file for reading. fopenw opens a new file for writing and fopena opens a new file for writing where any data .

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