TAILIEUCHUNG - Verilog Programming part 27

Tasks and functions are used to define common Verilog functionality that is used at many places in the design. | Summary In this chapter we discussed tasks and functions used in behavior Verilog modeling. Tasks and functions are used to define common Verilog functionality that is used at many places in the design. Tasks and functions help to make a module definition more readable by breaking it up into manageable subunits. Tasks and functions serve the same purpose in Verilog as subroutines do in C. Tasks can take any number of input inout or output arguments. Delay event or timing control constructs are permitted in tasks. Tasks can enable other tasks or functions. Re-entrant tasks defined with the keyword automatic allow each task call to operate in an independent space. Therefore re-entrant tasks work correctly even with concurrent tasks calls. Functions are used when exactly one return value is required and at least one input argument is specified. Delay event or timing control constructs are not permitted in functions. Functions can invoke other functions but cannot invoke other tasks. A register with name as the function name is declared implicitly when a function is declared. The return value of the function is passed back in this register. Recursive functions defined with the keyword automatic allow each function call to operate in an independent space. Therefore recursive or concurrent calls to such functions will work correctly. Tasks and functions are included in a design hierarchy and can be addressed by hierarchical name referencing. Team LiB Team LiB Exercises 1 Define a function to calculate the factorial of a 4-bit number. The output is a 32-bit value. Invoke the function by using stimulus and check results. 2 Define a function to multiply two 4-bit numbers a and b. The output is an 8-bit value. Invoke the function by using stimulus and check results. 3 Define a function to design an 8-function ALU that takes two 4-bit numbers a and b and computes a 5-bit result out based on a 3-bit select signal. Ignore overflow or underflow bits. Select Signal .

• Kỹ thuật lập trình
• thủ thuật lập trình
• tài liệu lập trình
• kĩ năng lập trình
• mẹo lập trình
• hướng dẫn lập trình
• Verilog Programming
• kỹ thuật lập trình
• kỹ năng lập trình
• bí quyết lập trình
• phương pháp lập trình
• tư liệu lập trình
• kĩ thuật lập trình
• AutoIT