TAILIEUCHUNG - Sequential Verulog Topics part 10

Verilog HDL Synthesis For the purpose of logic synthesis, designs are currently written in an HDL at a register transfer level (RTL). The term RTL is used for an HDL | Verilog HDL Synthesis For the purpose of logic synthesis designs are currently written in an HDL at a register transfer level RTL . The term RTL is used for an HDL description style that utilizes a combination of data flow and behavioral constructs. Logic synthesis tools take the register transfer-level HDL description and convert it to an optimized gate-level netlist. Verilog and VHDL are the two most popular HDLs used to describe the functionality at the RTL level. In this chapter we discuss RTL-based logic synthesis with Verilog HDL. Behavioral synthesis tools that convert a behavioral description into an RTL description are slowly evolving but RTL-based synthesis is currently the most popular design method. Thus we will address only RTL-based synthesis in this chapter. Verilog Constructs Not all constructs can be used when writing a description for a logic synthesis tool. In general any construct that is used to define a cycle-by-cycle RTL description is acceptable to the logic synthesis tool. A list of constructs that are typically accepted by logic synthesis tools is given in Table 14-1. The capabilities of individual logic synthesis tools may vary. The constructs that are typically acceptable to logic synthesis tools are also shown. Table 14-1. Verilog HDL Constructs for Logic Synthesis Construct Type Keyword or Description Notes ports input inout output parameters parameter module definition module signals and variables wire reg tri Vectors are allowed instantiation module instances primitive gate instances . mymux m1 out i0 i1 s . nand out a b functions and tasks function task Timing constructs ignored procedural always if then else initial is not supported case casex casez procedural blocks begin end named blocks disable Disabling of named blocks allowed data flow assign Delay information is ignored loops for while forever while and forever loops must contain @ posedge clk or @ negedge clk Remember that we are providing a cycle-by-cycle

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