TAILIEUCHUNG - Sequential Verulog Topics part 8

Internal Data Representation Before we understand how to use PLI library routines, it is first necessary to describe how a design is viewed internally in the simulator. Each module is viewed | Internal Data Representation Before we understand how to use PLI library routines it is first necessary to describe how a design is viewed internally in the simulator. Each module is viewed as a collection of object types. Object types are elements defined in Verilog such as Module instances module ports module pin-to-pin paths and intermodule paths Top-level modules Primitive instances primitive terminals Nets registers parameters specparams Integer time and real variables Timing checks Named events Each object type has a corresponding set that identifies all objects of that type in the module. Sets of all object types are interconnected. A conceptual internal representation of a module is shown in Figure 13-3. Figure 13-3. Conceptual Internal Representation a Module Each set contains all elements of that object type in the module. All sets are interconnected. The connections between the sets are bidirectional. The entire internal representation can be traversed by using PLI library routines to obtain information about the module. PLI library routines are discussed later in the chapter. To illustrate the internal data representation consider the example of a simple 2-to-1 multiplexer whose gate level circuit is shown in Figure 13-4. Figure 13-4. 2-to-1 Multiplexer The Verilog description of the circuit is shown in Example 13-1. Example 13-1 Verilog Description of 2-to-1 Multiplexer module mux2_to_1 out i0 i1 s output out output port input i0 i1 input ports input s wire sbar y1 y2 internal nets Gate Instantiations not n1 sbar s and a1 y1 i0 sbar and a2 y2 i1 s or o1 out y1 y2 endmodule The internal data representation for the 2-to-1 multiplexer is shown in Figure 13-5. Sets are shown for primitive instances primitive instance terminals module ports and nets. Other object types are not present in this module. Figure 13-5. Internal Data Representation of 2-to-1 Multiplexer The example shown above does not contain register integers module instances and other .

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