TAILIEUCHUNG - Sequential Verulog Topics part 7

UDP Table Shorthand Symbols Shorthand symbols for levels and edge transitions are provided so UDP tables can be written in a concise manner. | UDP Table Shorthand Symbols Shorthand symbols for levels and edge transitions are provided so UDP tables can be written in a concise manner. We already discussed the symbols and -. A summary of all shorthand symbols and their meaning is shown in Table 12-1. Table 12-1. UDP Table Shorthand Symbols Shorthand Symbols Meaning Explanation 0 1 x Cannot be specified in an output field b 0 1 Cannot be specified in an output field - No change in state value Can be specified only in output field of a sequential UDP r 01 Rising edge of signal f 10 Falling edge of signal P 01 0x or x1 Potential rising edge of signal n 10 1x or x0 Potential falling edge of signal Any value change in signal Using the shorthand symbols we can rewrite the table entries in Example 12-9 on page 263 as follows. table d clock clear q q 1 f 0 output 0 if clear 1 - ignore negative transition of clear 1 f 0 1 latch data on negative transition of 0 f 0 0 clock 1x 0 - hold q if clock transitions to unknown state p 0 - ignore positive transitions of clock 0 - ignore any change in d when clock is steady endtable Note that the use of shorthand symbols makes the entries more readable and more concise. Team LiB Team LiB Guidelines for UDP Design When designing a functional block it is important to decide whether to model it as a module or as a user-defined primitive. Here are some guidelines used to make that decision. UDPs model functionality only. They do not model timing or process technology such as CMOS TTL ECL . The primary purpose of a UDP is to define in a simple and concise form the functional portion of a block. A module is always used to model a complete block that has timing and process technology. A block can modeled as a UDP only if it has exactly one output terminal. If the block to be designed has more than one output it has to be modeled as a module. The limit on the maximum number of inputs of a UDP is specific to the Verilog simulator being used. However Verilog simulators are .

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