TAILIEUCHUNG - Verilog Programming part 24

A behavioral description expresses a digital circuit in terms of the algorithms it implements. A behavioral description does not necessarily include the hardware implementation details. Behavioral modeling | Summary We discussed digital circuit design with behavioral Verilog constructs. A behavioral description expresses a digital circuit in terms of the algorithms it implements. A behavioral description does not necessarily include the hardware implementation details. Behavioral modeling is used in the initial stages of a design process to evaluate various design-related trade-offs. Behavioral modeling is similar to C programming in many ways. Structured procedures initial and always form the basis of behavioral modeling. All other behavioral statements can appear only inside initial or always blocks. An initial block executes once an always block executes continuously until simulation ends. Procedural assignments are used in behavioral modeling to assign values to register variables. Blocking assignments must complete before the succeeding statement can execute. Nonblocking assignments schedule assignments to be executed and continue processing to the succeeding statement. Delay-based timing control event-based timing control and level-sensitive timing control are three ways to control timing and execution order of statements in Verilog. Regular delay zero delay and intra-assignment delay are three types of delay-based timing control. Regular event named event and event OR are three types of event-based timing control. The wait statement is used to model level-sensitive timing control. Conditional statements are modeled in behavioral Verilog with if and else statements. If there are multiple branches use of case statements is recommended. casex and casez are special cases of the case statement. Keywords while for repeat and forever are used for four types of looping statements in Verilog. Sequential and parallel are two types of blocks. Sequential blocks are specified by keywords begin and end . Parallel blocks are expressed by keywords fork and join. Blocks can be nested and named. If a block is named the execution of the block can be disabled from anywhere in

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