TAILIEUCHUNG - 80C51 Family Architecture

Tham khảo tài liệu '80c51 family architecture', công nghệ thông tin, tin học văn phòng phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | Philips Semiconductors 80C51 Family 80C51 family architecture 80C51 ARCHITECTURE The interrupt service locations are spaced at 8-byte intervals: 0003H for External Interrupt 0, 000BH for Timer 0, 0013H for External Interrupt 1, 001BH for Timer 1, etc. If an interrupt service routine is MEMORY ORGANIZATION short enough (as is often the case in control applications), it can All 80C51 devices have separate address spaces for program and reside entirely within that 8-byte interval. Longer service routines data memory, as shown in Figures 1 and 2. The logical separation of can use a jump instruction to skip over subsequent interrupt program and data memory allows the data memory to be accessed locations, if other interrupts are in use. by 8-bit addresses, which can be quickly stored and manipulated by an 8-bit CPU. Nevertheless, 16-bit data memory addresses can also The lowest 4k bytes of Program Memory can either be in the on-chip be generated through the DPTR register. ROM or in an external ROM. This selection is made by strapping the EA (External Access) pin to either VCC, or VSS. In the 80C51, if the Program memory (ROM, EPROM) can only be read, not written to. EA pin is strapped to VCC, then the program fetches to addresses There can be up to 64k bytes of program memory. In the 80C51, the 0000H through 0FFFH are directed to the internal ROM. Program lowest 4k bytes of program are on-chip. In the ROMless versions, all fetches to addresses 1000H through FFFFH are directed to external program memory is external. The read strobe for external program ROM. memory is the PSEN (program store enable). If the EA pin is strapped to VSS, then all program fetches are Data Memory (RAM) occupies a separate address space from directed to external ROM. The ROMless parts (8031, 80C31, etc.) Program Memory. In the 80C51, the lowest 128 bytes of data must have this pin externally strapped to VSS to enable them to memory are on-chip. Up to 64k bytes of external RAM can be execute from

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