TAILIEUCHUNG - Design and Implementation of 64 bit rISC processor using system on Chip (SOC)

In this paper, we present the design and implementation of a 64-bit reduced instruction set (RISC) processor with built-in-self test (BIST) features. | ISSN::2249-5789 1 Y B N V Bhaskar et al, International Journal of Computer Science & Communication Networks,Vol 2(1), 1-11 Design and Implementation of 64 Bit RISC Processor Using System on Chip (SOC) Y. B. N. V. Bhaskar Department of ECE Sri Vasavi Engineering College Tadepalligudem, Andhra Pradesh D. Rajesh Setty Associate Professor Department of ECE Sri Vasavi Engineering College Tadepalligudem, Andhra Pradesh Addanki Purna Ramesh Associate Professor Department Of ECE Sri Vasavi Engg College Tadepalligudem , India 534101 purnarameshaddanki@ Abstract In this paper, we present the design and implementation of a 64-bit reduced instruction set (RISC) processor with built-in-self test (BIST) features. A built-in self-test (BIST) or built-in test (BIT) is a mechanism that permits a machine to test itself. Key features of the design including its architecture, data path, and instruction set are presented. The design is implemented using VERILOG and verification is done on IUS (CADENCE) simulator. The proposed design may find applications where automation and control is required, say, in bottling plants and control of robotic movements. Illustrations highlight the typical use of our processor in bottling plants using exhaustive simulations. Future applications may include its use in vending machines, ATMs, mobile phones, and Portable gaming kits. Keywords RISC, BIST, BIT, VERILOG, IUS. 1. Introduction In today‟s Integrated Circuits (ICs), Built-InSelf Test (BIST) is becoming increasingly important as designs become more and more complicated. Keeping the structural fault coverage high along with maintaining an acceptable design overhead is critical. It is important to achieve a high level of reliability with minimum cost and time. It is with this goal in mind that BIST has become a major design consideration in Design-For-Testability (DFT) methods. BIST is beneficial in many ways: First, it can reduce dependency on external Automatic Test Equipment .

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