TAILIEUCHUNG - Lecture VLSI Digital signal processing systems: Chapter 13 - Keshab K. Parhi

Chapter 13 - Bit level arithmetic architectures. This chapter includes content: Parallel multipliers, parallel multiplication with sign extension, baugh-wooley multipliers, parallel multipliers with modified booth recoding, interleaved floor-plan and bit-plane-based digital filters, design of bit-serial multipliers using systolic mappings,. | Chapter 13: Bit Level Arithmetic Architectures Keshab K. Parhi • A W-bit fixed point two’s complement number A is represented as : A= where the bits ai, 0 ≤ i ≤ W-1, are either 0 or 1, and the msb is the sign bit. • The value of this number is in the range of [-1, 1 – 2-W+1 ] and is given by : A = - aw-1 + Σ aw-1-i2-i • For bit-serial implementations, constant word length multipliers are considered. For a W×W bit multiplication the W most-significant bits of the (2W-1 )-bit product are retained. Chap. 13 2 • Parallel Multipliers : A = = -aw-1 + B = = -bw-1 + W −1 ∑ i =1 W −1 ∑ i =1 aw-1-i2-i bw-1-i2-i Their product is given by : 2W − 2 P = -p 2W-2 + i∑1 p2W-2-i2-i = In constant word length multiplication, W – 1 lower order bits in the product P are ignored and the Product is denoted as XW⇐ P = A × B, where −1 X = -xW-1 + i∑1 xw-1-i2-i = Chap. 13 3 • Parallel Multiplication with Sign Extension : Using Horner’s rule, multiplication of A and B can be written as P = A × (-bW-1 + Σ bW-1-i2-i) = -A. bW-1 + [A. bW-2 + [A. bW-3 +[ + [A. b1 + A b0 2-1] 2-1] ]2-1] 2-1 where 2-1 denotes scaling operation. • In 2’s complement, negating a number is equivalent to taking its 1’s complement and adding 1 to lsb as shown below: W −1 − A = aw − 1 − i∑1 aw − 1 − i 2 −i = W −1 W −1 = aw − 1 + i∑1 (1 − aw − 1 − i ) 2 − i∑1 2 −i = = −i W −1 = aw − 1 + i∑1 (1 − aw − 1 − i ) 2 −i − 1 + 2 −W +1 = = −(1 − aw − 1) + Chap. 13 W −1 ∑ (1 − aw − 1 − i )2 i =1 −i + 2 −W +1 4 Tabular form of bit-level array multiplication • The additions cannot be carried out directly due to terms having negative weight. Sign extension is used to solve this problem. For example, A = a3 + a22-1 + a12-2 + a02-3 = -a32 + a3 + a22-1 + a12-2 + a 02-3 = -a322 + a32 + a3 + a 22-1 + a12-2 + a02-3 describes sign extension of A by 1 and 2 bits. Chap. .

• Điện - Điện tử
• VLSI Digital signal processing systems
• Digital signal
• Digital signal processing
• DSP systems
• Bit level arithmetic architectures
• Parallel multipliers
• FIR Digital Filters
• Parallel processing
• Loop bound
• DSP programs
• Retiming formulation
• Applications of retiming
• Algorithm for unfolding
• Applications of unfolding
• Retiming for folding
• Systolic architecture design
• Projection vector
• Cook toom algorithm
• Fast convolution
• Algorithmic strength reduction
• Parallel FIR filters
• Adaptive filters
• Parallel pecursive
• Round off noise
• State variable description
• Redundant arithmetic
• Redundant number representations
• Numerical strength reduction
• Multiple constant multiplication
• Low power design
• Programmable DSPs
• DSP applications