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ECE 551 Digital Design And Synthesis: Lecture 7 has many contents: Setting Basic Timing Constraints, Defining Input Delay, Anything More Need Constraints, GUI’s are for Children, Sample DC Shell Script, Hold time (worst case is back to back FF’s), Holy Mackerel Batmat, This thing is a monster, Getting Lost in a Sea of Documentation, Optimization Priorities, Constraints Default Cost Vector, Compiling the Design,. | ECE 551 Digital System Design & Synthesis Synthesis Synthesis Priorities First there is functionality Is function coded in Verilog same as synthesized netlist? Boolean correct Sequential correct No uninteded latches or strange clock gating Next there are design rules Is the fanout reasonable. Are my transition times fast enough (Hot Electron) Finally there are performance criteria Speed Power Area Synthesis is cost function driven Cost is a function of: Timing Area Power In this priority order Cost(mapping) = -Slack(mapping) + Area(mapping) + [power(mapping)] Explore mapping space to minimize this function (not the exact function) Mapping refers to the mapping of the logic (elaborated data base) to the cell library Synopsys is a bit like the typical ECE Student Smart, but a touch lazy Loose Constraints Loose Design What Needs Constraint? Combinational Combinational Combinational clk primary inputs primary outputs input to D delays Q to output delays clk cycle time input delay output delay Setting Basic Timing Constraints Establishing clock period, waveform, and pin it is sourced to: create_clock -name "clk" -period 20 -waveform { 0 10 } clk Name of clock, (a handle) not the pin it is sourced to Pin this clock is sourced to rise @ 0ns fall @ 10ns period = 20ns Clock is no ordinary input. Can’t let Synopsys buffer it and do other silly such things. If clock distribution requires buffering then that will be done by a separate tool (CTS) inside the APR environment. Defining Input Delay clk input delay Combinational source of input to DUT clk Combinational clk input delay is specified as time after the clock edge (of prior clock cycle) that the input to the DUT is valid. DUT t – input_delay Defining Output Delay clk output delay Combinational clk Combinational clk output delay is specified as time prior to next rising edge that the output has to be valid. DUT t – output_delay What Else Needs Constraint? in out tPHL in out in out tPHL . | ECE 551 Digital System Design & Synthesis Synthesis Synthesis Priorities First there is functionality Is function coded in Verilog same as synthesized netlist? Boolean correct Sequential correct No uninteded latches or strange clock gating Next there are design rules Is the fanout reasonable. Are my transition times fast enough (Hot Electron) Finally there are performance criteria Speed Power Area Synthesis is cost function driven Cost is a function of: Timing Area Power In this priority order Cost(mapping) = -Slack(mapping) + Area(mapping) + [power(mapping)] Explore mapping space to minimize this function (not the exact function) Mapping refers to the mapping of the logic (elaborated data base) to the cell library Synopsys is a bit like the typical ECE Student Smart, but a touch lazy Loose Constraints Loose Design What Needs Constraint? Combinational Combinational Combinational clk primary inputs primary outputs input to D delays Q to output delays clk cycle time input .
