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ECE 551 Digital Design And Synthesis: Lecture 3 has many content: Simulator Mechanics, Testbench Basics (stimulus generation), Dataflow Verilog, Analog Simulation (Spice Engine), Event-Driven Simulation, Digital Simulation, Testbench Requirements, Output Test Info, Output Format Strings, Output Example, Do ModelSim Example Here, Dataflow Verilog,. | ECE 551 Digital Design And Synthesis Fall ‘09 Simulator Mechanics Testbench Basics (stimulus generation) Dataflow Verilog Administrative Matters Readings Text Chapter 6 (Dataflow Verilog, vector concatenation, operators) Synthesis Tutorial coming in couple of weeks HW2 assigned posted Analog Simulation (Spice Engine) Divide “time” into slices Update information in whole circuit at each slice Used by SPICE Allows detailed modeling of current and voltage Computationally intensive and slow Don’t need this level of detail for most digital logic simulation Digital Simulation Don’t even need to do that much work! 0 0 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 1 0 1 1 1 Could update just the full path on input change 0 0 0 1 0 0 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 Could update every signal on an input change Event-Driven Simulation When an input to the simulating circuit changes, put it on a “changed” list When the “changed” list is empty: Keep simulation results Advance simulation time to next stimulus (input) event Loop while the “changed” list isn’t empty: Remove a signal from the “changed” list For each sink of the signal Recompute its new output(s) For any output(s) that have changed value, add that signal to the “changed” list Simulation Update only if changed Some circuits are very large Updating every signal => very slow simulation Event-driven simulation is much faster! 0 0 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 1 0 1 1 1 Testbench Basics (stimulus generation) Need to verify your design “Design Under Test” (DUT) Use a “testbench” Special Verilog module with no ports Generates or routes inputs to the DUT For now we will monitor outputs via human interface Stimulus DUT Inputs Inputs Outputs Outputs DUT OR Testbench Testbench (Response) (Response) Simulation Example adder4bit (DUT) a[3:0] b[3:0] sum[3:0] c_out 4 4 c_in 4 adder4bit_tb Use a consistent naming convention for your test benches: I usually add _tb to the end of the unit name adder4bit (DUT) a[3:0] . | ECE 551 Digital Design And Synthesis Fall ‘09 Simulator Mechanics Testbench Basics (stimulus generation) Dataflow Verilog Administrative Matters Readings Text Chapter 6 (Dataflow Verilog, vector concatenation, operators) Synthesis Tutorial coming in couple of weeks HW2 assigned posted Analog Simulation (Spice Engine) Divide “time” into slices Update information in whole circuit at each slice Used by SPICE Allows detailed modeling of current and voltage Computationally intensive and slow Don’t need this level of detail for most digital logic simulation Digital Simulation Don’t even need to do that much work! 0 0 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 1 0 1 1 1 Could update just the full path on input change 0 0 0 1 0 0 1 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 Could update every signal on an input change Event-Driven Simulation When an input to the simulating circuit changes, put it on a “changed” list When the “changed” list is empty: Keep simulation results Advance simulation time to .
