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Standardized Functional Verification- P5:Every manager who brings a design to tape-out or who purchases IP must eventually face these questions. The ability to answer these questions based on quantitative analysis is both vital and yet elusive. In spite of the enormous technical advances made in IC development and verification software, the answers to these questions are still based largely on guesswork and hand waving. | 2.9 Variables of Condition 25 exceed some high-water mark so that the queue can be emptied more quickly and thereby prevent overflow. The prior example of a PCI-Express link width might also be considered to be an indirect condition. Such a condition could be classified either way as convenient for the verification software. Finally it is practical to consider not only those conditions that govern the operation of the target but also those that govern the operation of its external context. Considering both the internal conditions and the external conditions relevant to the target are necessary to ensure that the target is thoroughly exercised. For example a target residing on a shared bus might behave differently depending on the conditions established in the external bus arbiter that determine priorities for granting access. Similarly as a consequence of activity on this shared bus the arbiter itself might enter an indirect condition such that priority for access to the bus is temporarily changed to favor some other bus-resident agent that is temporarily starved for bus bandwidth. To ensure that a target responds as expected to all defined stimuli it should be exercised with a carefully chosen subset or perhaps all of the combinations of defined conditions both internal and external. Choosing the values of the internal conditional variables determines the operation of an instance within its context. The process of establishing the initial operational conditions is called initialization. 2.9.1 Example - Conditions Consider the operation of the processor IP from our previous examples. see Fig. 2.5 It is designed to be flexible in its attachment to the system bus having either 32 bits or 64 bits for address and data. It can also be set up to operate in big-endian or little-endian mode. An internal prefetch controller can be enabled or disabled under control of a software-writable bit. Finally the store queue has a software-adjustable high-water mark that determines .
